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Ultra Accelerator Link (UALink) is an open specification for a die-to-die interconnect and serial bus between AI accelerators. It is co-developed by AMD, Astera Labs, AWS, Cisco, Google, Hewlett Packard Enterprise, Intel, Meta, and Microsoft.

UALink officially incorporated as an organization in 2024, and its first specification will provide interconnectivity specifically for a scale-up network. The initial 1.0 version 200Gbps UALink specification enables the connection of up to 1K accelerators within an AI pod, and is based on the IEEE P802.3dj PHY Layer. The specification was due to be available to Contributor Members in 2024, and will be released to the public during the first quarter of 2025.

References

1. Astera Labs webpage
2. "UALink Members UCIe". ualinkconsortium.org. Retrieved 2024-11-01.
3. "ABOUT UALINK". UALink Consortium. Retrieved 2025-01-20.

See also

• Ethernet
• Infinity Fabric
• NVLink

External links

• Official website

• Computer-related introductions in 2024
• Open standards
• Serial buses